About this project
silicon architect is an MCP server that gives AI coding assistants a real, evidence-based semiconductor design toolchain — not simulated output. It runs actual RTL elaboration and formal bounded model checking via a WebAssembly build of Yosys, performs genuine sky130 standard-cell synthesis with measured cell area, and executes real FPGA place-and-route with nextpnr for ECP5 and iCE40, reporting achieved Fmax rather than estimates. Layered on top are IP discovery, revision history, netlist graph visualization, auto-generated design reports, and a transparent cost sheet, so an AI client can choose its next tool based on what the previous one actually produced. The result: fewer manual handoffs between specialist EDA tools, earlier detection of RTL defects before they become costly downstream, and an auditable, evidence-backed workflow that gives smaller teams and startups access to professional chip-design capability — all while keeping engineers in the loop reviewing real outputs, not AI-generated guesses.
Enterprise AI & Workplace Automation track
Develop AI agents and automation tools that improve productivity, streamline workflows, and enhance business operations.
Team ZeroOne [amFOSS]
Saharsh Baiju